1. Field of the Invention
The present invention relates to a source line driver, and in particular to a source line driver for a flash memory capable of driving sources lines while occupying a relatively small area of the flash memory.
2. Description of the Related Art
FIG. 1 is a basic structure diagram of a conventional flash memory. The flash memory is composed of a plurality of memory cells for memorizing and other control components. The memory cells 100,0 . . . 102n−1,m−1 are disposed in an array and constitute a memory array 10. Each memory cell (as labeled “101” in FIG. 1) has a memory transistor to store logic level “1” or “0”. In the memory array 10, each word line selects the memory cells in a column. When receiving a row address signal, a word line decoder 11 enables one word line to select the memory cells in the corresponding row. When receiving a column address signal, a bit line decoder 12 drives one bit line to select the memory cells in the corresponding column. According to the row address signal and the column address signal, a selected memory cell can execute read, program, and erase operations. Moreover, as shown in FIG. 1, source lines SL10. . . SL1n−1 are coupled to a source line driver 13 and extend therefrom in the direction of the word line decoder 11. Each source line applies voltage to the memory cells in two corresponding rows. For example, the memory cells 100,0 . . . 100,m−1 and 101,0 . . . 101,m−1 are coupled to the source line SL10 and receive voltage therefrom. In the read, program or erase operations, different states of the source line driver 13.
FIG. 2 shows an equivalent circuit of the memory units of the conventional flash memory, the memory cells 100,0 and 100,1 are taken as an example. Control gates of memory cells 100,0 and 100,1 are respectively coupled to the word lines WL10 and WK11, both drain terminals thereof are coupled to the bit line BL10 and WL11, both drain terminals thereof terminals thereof are coupled to the source line SL10. The source line SL10 applies voltage to the memory cells 100,0 and 100,1.
FIG. 3 is a schematic diagram of the conventional source line driver of the conventional flash memory. As shown in FIG. 3, the source line driver 13 comprises a plurality of source line driving units, and one source line driving unit controls one source line. Each source line driving unit comprises three portions.
Taking the source line driving unit 130 as an example, the source line driving unit 130 controls the source line SL10 applying voltage to the memory cells 100,0 . . . 100,m−1 and 101,0 . . . 101,m−1. The source line driving unit 130 comprises a first circuit 1310 having transistor N130, N140, and N150, a second circuit 1320, serving as a latch circuit, having inverter I110 and I120, and a third circuit 1330 having transistor N110 and N120. Because a gate of the transistor N110 is coupled to a voltage source VDD1 having a VDD, the transistor N110 remains turned on. VDD is the operating voltage of the core circuit, which can be 3.3 V, 2.5 V, or 1.8 V in a semiconductor manufacture process. Also VDD is not the program voltage having a value between 10 V to 12 V.
In read and erase operations N130 turns off due to P1 having GND level. When word lines are not selected during program operation, the transistors N140 and N150 are turned off. A gate of the transistor N120 receives a signal PL1 having a VDD to turn on the transistor N120. Therefore, the source line SL10 is coupled to a ground GND1 through the transistors N110 and N120. In read operation, in order to read data, the gate of the transistor N120 receives the signal PL1 having a VDD to turn on the transistor N120, the source line SL10 is coupled to the ground GND1 through the transistors N110 and N120.
Furthermore, where the memory cell 100,0 is assigned to execute program operation, the word line WL10 and the signal P1 are at a VDD to respectively turn on the transistors N150 and N130. A voltage level of an inverting source line SLB10 is pulled down to the low voltage level of the ground GND1 by the transistor N150 and N130 within the first circuit 1310. The source line SL10 is latched at a high voltage level of a voltage source VPP1 through the latch circuit comprising the inverter I110 and I120. In addition, because the gate of the transistor N120 receives the signal PL1 having a GND, the turned-off transistor N120 isolates the ground GND1 and the source line SL10. Therefore, the source line SL10 is at a high voltage level and the memory cell 100,0 can execute program operation.
As described above, each third circuit within the source line driving units comprises two transistors for controlling the voltage level of the corresponding source line and further controlling the corresponding memory cells.
Generally, the total size of the third circuits is proportional to the number of data input/output ports. That is, the size of the flash memory increases along with the increase of the number of data input/output ports. Recently, flash memory used for Field Programmable Gate Array (FPGA) applications require very wide data input/output buses. The cascade transistor structure of the third circuits within the source line driving units occupies a large area in a conventional flash memory.